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ISL6592
Data Sheet August 5, 2005 FN9163.1
6-Phase Digital Multiphase Controller
The ISL6592 digital multiphase controller provides core power for today's high current microprocessors by driving up to six synchronous-rectified buck-converter channels in parallel. Interleaved timing of the channels results in a higher ripple frequency, reducing input and output ripple. With up to six phases, each capable of up to 1.5MHz operation, the ISL6592 can be used to build DC/DC converters that provide up to 200A with excellent efficiency, low ripple, and the lowest component count. The ISL6592 utilizes digital technology to implement all control functions, providing the ultimate in flexibility and stability. The ISL6592 incorporates an industry standard I2C serial interface for control and monitoring. Through the serial interface, the power supply designer can quickly optimize designs and monitor parameters. The interface allows the ISL6592 to provide digitized information for real time system monitoring and control. The ISL6592 provides superior loadline accuracy through internal calibration that measures and corrects current sense error sources upon start-up. The ISL6592 has programmable current sense temperature compensation that allows the designer to tailor the response for best loadline accuracy over temperature. Superior loadline accuracy reduces component count and solution cost. To further reduce component count the ISL6592 incorporates patented Active Transient Response (ATR) technology, allowing the fastest response to transient events for reduced output capacitance. The flexibility of the ISL6592 allows the power supply designer to implement a wide range of solutions. When used with industry standard power train components, ISL6592 provides the highest performance with lowest component count and cost. When area is at a premium, ISL6592 can be used with the ISL6597 integrated power stage to implement the industry's highest density power solutions.
Features
* Multiphase power conversion - 2- to 6-phase operation * 300kHz to 1.5MHz switching frequency * Supports Intel(R) VR 10.x, AMD(R), and custom VID codes * Internal high precision voltage reference - 5mV voltage setpoint accuracy * Precision digital current sense calibration - 14mV loadline accuracy * Precise digital current balancing with programmable offsets for thermal balancing * Digitally programmable loadline and loop compensation * Differential voltage sense * Digital temperature sensor compensation * Active Transient Response (ATR) enables meeting transient requirements with reduced output capacitance * I2C interface for monitoring, control and configuration * Internal non-volatile memory (NVM) to store custom configurations with four programmable system configurations * Extensive fault detection capability with two user configurable output fault pins - Input Undervoltage - Output Under/Overvoltage - High Side Short - Per Phase and Total Output Current - Multiple Internal and External Temperature Limits - -NVM Configuration - Calibration Range and Time-Out * Configurable latched fault or autonomous recovery shutdown * Single +3.3V supply operation * 48 lead LQFP plastic package
Ordering Information
PART NUMBER ISL6592DNZ-T (Note) TEMP. RANGE (C) 0 to 85 PACKAGE 48 Ld 7x7 LQFP (Pb-free) PKG. DWG. # Q48.7x7A
* Commercial temperature range of 0C to 85C ambient * Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
* Core power regulation for Intel(R) and AMD(R) mprocessors * Intelligent point-of-load (POL) power regulation
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL6592 Pinout
ISL6592 (LQFP) TOP VIEW
CAL_CUR_SEN 38
CAL_CUR_EN 39
TCLK_SEL
48
47
46
45
44
43
42
41
40
37
RESET_N 36 35 34 33 32 31 30 29 28 27 26 25
FAULT2
FAULT1
SADDR
VD25
SDA
SCL
LL1
LL0
GND VID4 VID3 VID2 VID1 VID0 VID5 OUTEN VCC_PWRGD OUT12 OUT11 VDD
1 2 3 4 5 6 7 8 9
VDD ISEN6 ISEN5 ISEN4 ISEN3 ISEN2 ISEN1 TEMP_SEN VBG_EXT VSENP VSENN GND
10 11 13 14 15 16 17 18 19 20 21 22 OUT1 23 V12_SEN 12
OUT9
OUT8
OUT7
OUT6
OUT5
OUT4
OUT3
2
OUT10
OUT2
VDD
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FN9163.1 August 5, 2005
ISL6592 Block Diagram
VSENP VSENN RESET_N
POR
Window Com parator (OVP/UVP)
OUT12
Voltage ADC
OUT11 OUT10 OUT9 OUT8
ISEN1 ISEN2 ISEN3 ISEN4 ISEN5 ISEN6 TEMP_SEN V12_SEN SCL SDA SADDR
I2C Inte rnalM e m ory Fault Handle r Temp Se ns e Curre nt Se ns e Curre nt ADC Channel Current AVP Current Balance PID/PWM Controller
PWM Drive r
OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 OUT1 FAULT1 FAULT2
VID4 VID3 VID2 VID1 VID0 VID5 OUTEN LL0 LL1 VCC_PWRGD
Deglitch State M achine DigitalCalibration Controlle r
CAL_CUR_SEN CAL_CUR_EN
FIGURE 1. TOP LEVEL BLOCK DIAGRAM
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ISL6592 Typical VRM Application
+8V to +12V +5V to +12V
VDRIVE PWM V CC VSW
ISL6597
NDRIVE HSS
NGATE G ND
VDRIVE
V CC VSW
+3.3V
VDD
V12_SEN GND OUT1 OUT2 ISEN1 OUT3 OUT4 ISEN2 OUT5 OUT6 ISEN3 OUT7 OUT8
PWM
ISL6597
ISL6592
VID4 VID3 VID2
NDRIVE HSS
NGATE G ND
VDRIVE PWM
V CC VSW
ISL6597
From P
VID1 VID0 VID5 LL0 LL1 OUTEN
NDRIVE HSS
NGATE G ND
VDRIVE PWM
V CC VSW
ISL6597
NDRIVE HSS
NGATE G ND
Vout RTN
To P
VCC_PWRGD
ISEN4 OUT9 OUT10 ISEN5
VDRIVE PWM V CC VSW
ISL6597
NDRIVE HSS
NGATE G ND
Fault Outputs
FAULT1 FAULT2
OUT11 OUT12 ISEN6
VDRIVE PWM
V CC VSW
I2CI/F Bus
SDA SCL SADDR
TEMP_SEN CAL_CUR_EN CAL_CUR_SEN VSENP VSENN
ISL6597
NDRIVE HSS
NGATE G ND RTHERM
Crowbar Control (optional)
FIGURE 2. 6-PHASE VRM DESIGN WITH ISL6597
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ISL6592
D
Absolute Maximum Ratings
Supply Voltage (VDD) . . . . . . . . . . . . . . . . . . . . . . . -0.50V to 4.25V All pins except ISENx and ground . . . . . . . . . . . . . . -0.50V to 4.25V All ISENx pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.50V to 3.0V All ground pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.50V to 0.50V Differential Voltage (VSEN_DIFF) . . . . . . . . . . . . . . . . . . . . . . . . 2.5V ESD Rating Human Body Model (Per MIL-STD-883 Method 3015.7) (100pF, 1.5k) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3,000V Charged Device Model (Per EOS/ESD DS5.3, 4/14/93) . . 1,000V Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300V
Thermal Information
Thermal Resistance (Typical, Note 1) JA (C/W) TQFP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Maximum Storage Temperature Range . . . . . . . . . . . -65C to 150C Maximum Junction Temperature Range . . . . . . . . . . . 0C to 125C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300C
Operating Conditions
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . 0C to 85C Supply Voltage Range (Typical). . . . . . . . . . . . . . . . +3.0V to +3.6V
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
PARAMETER VDD SUPPLY Nominal supply current VID[5:0] INPUTS (Note 4) Input low voltage Input high voltage Input current (input voltage low) Input current (input voltage high) OUTEN INPUT Input low voltage Input high voltage Input current (input voltage low) Input current (input voltage high) LL[1:0] INPUTS Input low voltage Input high voltage Input current (input voltage low) Input current (input voltage high) SDA, SCL INPUTS Input low voltage Input high voltage Input current, input voltage low Input current, input voltage high Output low voltage
VDD = +3.3V, TC = +85C, unless otherwise specified SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
IVDD
VDD = +3.3V, ISEN[6:1] = -70A
100
140
mA
VIL_VID VIH_VID IIL_VID IIH_VID (Note 5) VIN = 0.0V VIN = 3.5V
-0.3 0.8 -75 -10
0.4 5.5 10 10
V V A A
VIL_OE VIH_OE IIL_OE IIH_OE OE = 0.0V OE = 3.5V
-0.3 0.8 -75 -10
0.4 5.5 10 10
V V A A
VIL_LL VIH_LL IIL_LL IIH_LL LL(X) = 0.0V LL(X) = 1.20V 0.8 -20 15
0.4
V V
-30 25
A A
VIL_S VIH_S IIL_S IIH_S VOL VIN = 0.0V VIN = 3.5V Open drain output, ILOAD = +5mA
-0.3 2.4 -10 -10
0.8 5.5 10 10 0.4
V V A A V
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ISL6592
Electrical Specifications
PARAMETER SADDR, RESET_N INPUTS Input low voltage Input high voltage Input current, input voltage low Input current, input voltage high VSENP, VSENN INPUTS VSENN voltage Bandwidth VSENP input current VSENN input current ISEN[6:1] INPUTS Input current range Bias voltage accuracy Input resistance Clamp voltage I-Sense amplifier linearity error INLSA RIN IIN = 20mA TA = 25C TA = 0 to 85C, (Note 6) Current conversion ADC error INLIADC TA = 25C TA = 0 to 85C, (Note 6) TEMP_SEN INPUT Bias Voltage Input Current Range Input resistance V12_SEN INPUT Voltage threshold CAL_CUR_SEN INPUT Sensed voltage RESET_N Input low voltage Input high voltage Input current, input voltage low Input current, input voltage high OUT[12:1] OUTPUTS (PWM, NDRIVE) Output low voltage Output high voltage Output current, output voltage Hi-Z FAULT1, FAULT2 Output low voltage Output current, output voltage Hi-Z VOL IOZ ILOAD = 5mA VOUT = 1.65V -10 0.4 10 V A VOL VOH IOZ ILOAD = +5mA ILOAD = -5mA VOUT = 1.65V 2.4 -10 10 0.4 V V A VIL VIH IIL IIH VIN = 0.0V VIN = 3.5V -0.3 2.4 -75 -10 0.8 3.6 -10 10 V V A A RSEN = 20 to 100m, ICAL = 2 to 10A 0.17 0.24 V VTH 0.91 1.09 V VBIAS IIN RIN IIN = -20A -275 200 295 -10 mV A 2.2 2 2 IIN Programmable from 25mV to 150mV -275 -18 100 1.65 1.6 -10 +18 A mV V % % % % IIN IIN VSENP = 1.6V VSENN = 0V -10 -10 VSENN (Note 6) 0.3 1.5 +10 +10 V MHz A A VIL_S VIH_S IIL_S IIH_S VIN = 0.0V VIN = 3.5V -0.3 2.8 -75 -10 0.5 3.6 -10 10 V V A A VDD = +3.3V, TC = +85C, unless otherwise specified (Continued) SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
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Electrical Specifications
PARAMETER VCC_PWRGD OUTPUT (Note 2) Output low voltage CAL_CUR_EN Output low voltage Output high voltage SETPOINT ACCURACY Setpoint accuracy VREF VID = 1.20V, TA = 25C VID = 0.85 to 1.60V, TA = 0 to 85C, (Note 6) Voltage conversion gain error GREF TA = 25C TA = 0 to 85C, (Note 6) Voltage conversion ADC error INL INLVADC TA = 25C TA = 0 to 85C, (Note 6) SWITCHING FREQUENCY Frequency accuracy FSW Range: 100kHz to 2MHz, (Note 7) TA = 25C VDD = +3.0V to +3.6V, TA = 0 to 85C, (Note 6) FAULT MONITORS IUVP lockout threshold (Note 3) OUVP threshold voltage (Note 3) OOVP threshold accuracy (Note 3) Internal OTP threshold range Internal OTP threshold accuracy NOTES: 2. Open drain output. Contains an active pull-down such that VCC_PWRGD < 0.8V with no +3.3V supplied. 3. Setting is programmable. 4. An open input will float to the logic-1 state. This feature is not intended as a replacement for an external pull-up resistor when the input is driven by an open-drain driver. 5. VIH(max) is guaranteed but not tested. Input current is typically less than 2mA at VIH = +5V. In applications requiring +5.5V tolerance, the device must be driven by an open drain or open collector source with a pull-up resistance of no less than 1k. 6. Guaranteed, but not tested in production. 7. Setting is programmable. 8. Guaranteed by calibration during production test. VIUVP VOUVP VOOVP Programmable from 0.225V to 1.80V (Note 8) See PTAT shut_down in Table 5 10 C 0.25V/LSB 2 0.49 -25 0.60 12 0.71 +25 V V mV -5 10 5 % % 9 0.75 8.5 8 10 0.5 mV mV % % mV mV VOL VOH ILOAD = +500A ILOAD = -1mA 2.8 0.4 V V VOL Open drain output, ILOAD = +5mA 0.4 V VDD = +3.3V, TC = +85C, unless otherwise specified (Continued) SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
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ISL6592 Pin Description
PIN # 1 2 3 4 5 6 7 8 NAME GND VID4 VID3 VID2 VID1 VID0 VID5 OUTEN I/O I I I I I I I I TYPE GND 1.2V CMOS 1.2V CMOS 1.2V CMOS 1.2V CMOS 1.2V CMOS 1.2V CMOS 1.2V CMOS Ground Bit 4 of processor voltage identification word (MSB) Bit 3 of processor voltage identification word Bit 2 of processor voltage identification word Bit 1 of processor voltage identification word Bit 0 of processor voltage identification word (LSB of 5-bit VID word) Bit 5 of processor voltage identification word (LSB of 6-bit VID word) Processor output enable input signal used to command the regulator output. "1" Regulator output voltage active "0" Regulator output voltage three-stated Digital Controller power good control output signal to indicate the regulator output voltage is within the specified range. "1" P VCC > 90% of target regulation voltage "0" P VCC < 90% of target regulation voltage Configurable PWM, NDRIVE, ATRH or ATRL output (see Table 3) Configurable PWM, NDRIVE, ATRH or ATRL output (see Table 3) 3.3V power supply connection Configurable PWM, NDRIVE, ATRH or ATRL output (see Table 3) Configurable PWM, NDRIVE, ATRH or ATRL output (see Table 3) Configurable PWM, NDRIVE, ATRH or ATRL output (see Table 3) Configurable PWM, NDRIVE, ATRH or ATRL output (see Table 3) Configurable PWM, NDRIVE, ATRH or ATRL output (see Table 3) Configurable PWM, NDRIVE, ATRH or ATRL output (see Table 3) Configurable PWM, NDRIVE, ATRH or ATRL output (see Table 3) Configurable PWM, NDRIVE, ATRH or ATRL output (see Table 3) Configurable PWM, NDRIVE, ATRH or ATRL output (see Table 3) Configurable PWM, NDRIVE, ATRH or ATRL output (see Table 3) 1/10 V12 voltage divider input. Used to guarantee valid input power supply before starting up (undervoltage lockout) 3.3V power supply connection Ground Negative regulator output voltage sense input. Positive regulator output voltage sense input. optional external bandgap voltage (not used) External thermistor temperature sense. Connected to ground through a negative TC thermistor, with series and shunt resistance added to achieve desired range. TEMP_SEN is held at 150mV, current through thermistor is measured by ADC. Effective ADC range is 0 - 275A in 4.3A steps. User should avoid using the 4 codes at the extremes in order to avoid clipping the ADC. ADC code is translated to temperature using an internal 4 segment piecewise linear lookup table. DESCRIPTION
9
VCC_PWRGD
O
Open Drain
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
OUT12 OUT11 VDD OUT10 OUT9 OUT8 OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 OUT1 V12_SEN VDD GND VSENN VSENP VBG_EXT TEMP_SEN
O O I O O O O O O O O O O I I I I I I O
3.3V CMOS 3.3V CMOS VDD 3.3V CMOS 3.3V CMOS 3.3V CMOS 3.3V CMOS 3.3V CMOS 3.3V CMOS 3.3V CMOS 3.3V CMOS 3.3V CMOS 3.3V CMOS Analog VDD GND Analog Analog Analog Analog
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ISL6592 Pin Description
PIN # 30 (Continued) I/O I TYPE Analog DESCRIPTION Phase channel #1 ADC current sense input. This pin is held at a virtual ground, with programmable offset from 25 to 300mV. An external sense resistor is connected to the drain of the low side FET so that its current may be determined. The current sourced from the input is given by: ISEN = (Voffset - VRDSON)/RSEN1. Input current is digitized with the ADC with an effective ADC range of 0 -275A in 4.3A steps. Phase channel #2 ADC current sense input. See ISEN1 for description. Phase channel #3 ADC current sense input. See ISEN1 for description. Phase channel #4 ADC current sense input. See ISEN1 for description. Phase channel #5 ADC current sense input. See ISEN1 for description. Phase channel #6 ADC current sense input. See ISEN1 for description. 3.3V power supply connection Active low asynchronous system reset to place ISL6592 into default state "1" asynchronous reset disabled "0" asynchronous reset enabled Calibration current sense input. Measures the voltage across the sense resistor. FET gate voltage is adjusted via an opamp loop such that the voltage across the resistor is set at 100mV. Calibration current enable output. Drives the calibration FET gate voltage to adjust its rDS(ON) such that voltage across the sense resistor is set at 100 mV. Programmable fault indicator #1 Programmable fault indicator #2 Tie to Ground for normal operation I2C address LSB select "1" 1110001 selected "0" 1110000 selected I2C interface serial data line. I2C interface serial clock line. Processor load line select input control signal (MSB). Selects regulator load line resistance. Processor load line select input control signal (LSB). Selects regulator load line resistance. Decoupling capacitor for 2.5V internally generated voltage 0.01F recommended, 0.1F max
NAME ISEN1
31 32 33 34 35 36 37
ISEN2 ISEN3 ISEN4 ISEN5 ISEN6 VDD RESET_N
I I I I I I I
Analog Analog Analog Analog Analog VDD 3.3V CMOS
38
CAL_CUR_SEN
I
Analog
39
CAL_CUR_EN
O
Analog
40 41 42 43
FAULT1 FAULT2 TCLK_SEL SADDR
O O I I
3.3V CMOS 3.3V CMOS 3.3V CMOS 3.3V CMOS
44 45 46 47 48
SDA SCL LL0 LL1 VD25
I I I I I
3.3V CMOS 3.3V CMOS 1.2V CMOS 1.2V CMOS Analog
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FN9163.1 August 5, 2005
ISL6592 General Description
The ISL6592 is a digital multi-phase pulse width modulation controller integrated circuit for use in 2- to 6-phase synchronous buck converter CPU core supply power switching regulators. The device is optimized for delivering voltages from 0.8 to 1.6V at high current levels (120A+) with programmable PWM switching frequencies between 300kHz and 1.5MHz. The ISL6592 brings the benefit of digital control to voltage regulators targeting Intel(R) VRD/VRM 10.x, AMD(R) VRM 1.05, and similar applications. The ISL6592 is designed to maximize value to the user by providing features, monitoring and performance to minimize the number of required off-chip components, work with a variety of widely available standard components, and to accommodate wider device tolerance mismatches than competing analog controller solutions. The ISL6592 provides both ease-of-use and flexibility to the user. Major features include: * Internal Voltage and Temperature Reference - An internal factory trimmed 0.5% voltage reference sets the VID DAC, voltage ADC and current ADC range. In addition, a proportional-to-absolute-temperature (PTAT) reference is generated and digitized to serve as the controller temperature sensor. * Internal Oscillator - Provides a factory trimmed 156.25MHz 10% clock reference. Fixed and programmable dividers generate all the needed internal clocks to configure the controller's switching frequency and number of active phases. * Dedicated Voltage ADC - A high precision differential input voltage ADC digitizes the differential remote sense voltage. An integrated anti-alias filter and ripple frequency null filter minimize the impact of high frequency noise on the system. * Multiplexed Current Sense ADC - The average currents from each phase are sensed as a voltage across the low side FET using the multiplexed current ADC. Each phase is sampled at the middle of its cycle, with timing optimized through a programmable delay line. The internal temperature reference and external thermistor temperature are also digitized using the multiplexed current ADC. Gain and offset of the sensor and ADC are compensated through either a one time factory calibration, or through a power-up calibration each time the output voltage is reset. * Digital Control Loop and AVP - An over-sampled digital Proportional-Integral-Derivative (PID) compensator provides flexible loop compensation with programmable coefficients. A digital post-filter provides additional phase lead and/or high frequency filtering to optimize the transient response and ripple of the system. A high accuracy Active Voltage Positioning (AVP) loadline is 10 computed using the calibrated current sense measurements. The AVP bandwidth is also programmable to allow it to be optimized for dynamic performance. * Window comparators - Window comparators with programmable thresholds to be set for overvoltage protection (OOVP) and high side short (HSS) detection. * Active Transient Response (ATR) - ATR comparators with programmable thresholds are used to provide fast response to dynamic load transients, minimizing spike overshoot and droop undershoot. * Configurable PWM Generators - 2-6 PWM waveforms are digitally generated ensuring low jitter and high linearity. PWM outputs are configurable as either single tri-valent outputs or dual outputs with programmable non-overlap delay. Phases can be fully overlapped, with programmable duty cycle limiting. * Integrated NVM - Digital configuration is stored in an integrated NVM, allowing fully independent (stand-alone) operation. NVM is fully accessible to user so that a completely new parameter set can be written. Vendor and user defined memory locations are provided, allowing version control and part identification. NVM integrity is checked every configuration cycle through a cyclic redundancy check (CRC) comparison. * Serial Interface - GUI software provides easy access to all configuration, telemetry, and testability features over a 2 wire I2C serial interface. The GUI interface allows full accessibility to regulator telemetry during system operation including: * Internal Controller Temperature * External (via optional thermistor) System Temperature * Per Phase Current * Total Output Current * Output Voltage * Input Voltage * Configurable latched and unlatched individual fault status * Microprocessor Leakage Current * User defined memory space Fault reporting and shutdown behavior are also fully configurable. Two individual fault outputs are provided, with all faults being independently maskable. The outputs can be configured as either latched or unlatched, active high or active low polarity, and CMOS or open drain outputs. The shutdown operation also allows all faults to be individually masked and for the shutdown operation to be either latched or unlatched. Individual status registers allow fault reporting
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ISL6592
over the serial bus to identify the specific fault event. Fault detection includes the following: * Input Undervoltage * Output Overvoltage * Output Undervoltage * High-side Short * Per Phase Overcurrent * Total Output Overcurrent * Two levels of Internal Temperature Protection * Two levels of External Temperature Protection * Configuration Failure * Calibration Range Failure * Calibration Time-out Failure The ISL6592 is also optimized for use with the ISL6597 integrated power stage to deliver a high performance VR solution. The ISL6597 offers the following benefits when combined with the ISL6592 controller: * Low delay, fast transition, low rDS(ON) (13m) integrated high side P-channel FET * Low delay, high drive (2A) low side N-channel FET driver * High accuracy, low drift integrated current mirror, allowing lossless current sensing with loadline accuracy comparable to series sense resistor solutions * Power supply sequence independence between the power input (12V), low side driver supply (5-12V), and controller supply (3.3V) * Direct high side short detect and crowbar capability, operates off the 12V input supply and is thus independent of controller power supply Please see the ISL6597 data sheet for more details on the performance, capability, and interface requirements of ISL6592/ISL6597 systems. may be low, high or three-state. During the inactive state, the controller can communicate over the serial bus, report configuration or inactive state faults (e.g. high side short). The controller will leave the inactive state and begin softstart once it has a valid VID, OEN is asserted, and the 12V power input is valid. The 12V input is sensed through a resistive divider on the board, and a programmable threshold comparator must be tripped if the input undervoltage lockout is enabled. The sense circuit can be easily modified to also sense an independent or sequenced lower drive voltage typically used to optimize the efficiency of the power stage low side FET.
Soft-Start and Calibration
Prior to entering an active regulating state, the ISL6592 performs a well-controlled, monotonic initial ramp or "softstart". Soft-start is performed by actively regulating the load voltage while digitally ramping the target voltage from 0 to the voltage set. During this time, the optional power-up system calibration can be performed. The calibration algorithm compensates for variations in low-side FET rDS(ON), parasitic inductance and resistance by regulating to a low voltage level, putting a known current load through each phase individually and compensating for the current sense gain and offset error, as well as changes in temperature. Alternatively, default compensation values can be used, or the compensation values can be computed during system test and stored in memory. The external current load needed to perform calibration can be implemented with a precision resistor and N-channel FET. The voltage across the resistor is sensed and the N-channel FET gate voltage is adjusted through an internal opamp loop to provide the desired precision current. The calibration current level and the voltage level at which the calibration is performed are both programmable. After the soft-start ramp is completed, the processor's leakage current is measured. At this point the regulator enters the active regulation state and the VCC_PWRGD pin transitions from "0" to "1," indicating that the microprocessor voltage is within 90% of the target value.
Theory of Operation
Power Up and Initialization
The ISL6592 is designed to provide supply sequence independence and graceful turn-on and turn-off operation. It operates from a single +3.3V supply, while an on-chip low drop-out (LDO) regulator generates an internal +2.5V supply. Power-up controller configuration is initialized by either an internal threshold based power-on reset, or by an external reset pin (RST_N). During controller configuration, the contents of the NVM are read into the controller's registers. During configuration, all outputs are three-stated, allowing board pull-up or pull-down resistors to set the correct default level. Once configuration is completed, the controller enters an inactive state. Outputs assume their default values, which 11
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ISL6592
is the programmable divider ratio between 6 and 127, and Nph is the number of phases between 2 and 6. Although switching frequencies of less than 300kHz and greater than 1.5MHz can be generated, various system optimization parameters may not have adequate range to optimize the loop outside this range.
Output Voltage Sensing and Voltage ADC
The ISL6592 is built around a high performance digital feedback control loop that senses the differential voltage at the load. This is used to generate the appropriate pulse width modulated (PWM) waveforms to drive the power stages and regulate the load voltage. The differential sense voltage is digitized with a high speed, high precision analog-to-digital converter (ADC). The onchip factory trimmed temperature compensated bandgap voltage reference ensures the ADC accuracy is well within the regulator setpoint accuracy requirements. The ADC is sampled synchronously so that there are 2 ADC samples per phase per switching cycle, at a frequency given by: Fs = 156.25MHz/div_sel The ADC also includes a post-filter which, when enabled, provides a null at Fsw * (Nph/2), which is the ripple frequency. This ripple null filter works in conjunction with an internal analog anti-alias filter. The anti-alias filter is a single pole, 2MHz low pass filter. The corner frequency can be lowered by adding series resistors in the board.
FIGURE 3. SOFT-START/CALIBRATION SEQUENCE (3-PHASE)
Shutdown
The ISL6592 also performs a controlled shutdown response to minimize any voltage undershoot. The shutdown state can be entered from the soft-start or active regulation states either through user intervention (de-asserting OEN or all one's VID), or through a detected fault such as overtemperature or output overvoltage. During shutdown, the PWM width is reduced at a steady programmable rate, and then the power stage is three-stated once the pulse width reaches 0. After shutdown is complete, the controller re-enters the inactive state after a fixed delay. This delay minimizes the duty cycle associated with autonomous restarts if the fault that caused the shutdown disappears once the output is disabled. Alternatively, the fault can be configured so that it is latched and clearing requires user intervention such as toggling OEN, toggling RESET_N, or cycling power.
Current Sensing and Current ADC
The ISL6592 provides for precise current monitoring in each power stage, allowing for industry-leading loadline accuracy for active voltage positioning (AVP). The current in each power stage is sensed by measuring the voltage across the bottom side FET in the middle of its on cycle. This voltage is digitized using a multiplexed current ADC. The current sense inputs (ISEN1 to ISEN6) are held at a virtual ground with programmable offset from 25mV to 200mV. The large voltage swing at the drain of the low side FET is eliminated by using a series resistor, converting the signal to a current equal to: Isense = (Voff - Vds)/Rsense where Isense is the current sourced by the sense input, Voff is the programmable offset, Vds is the voltage across the low side FET, and Rsense is an external resistor whose value is chosen to scale the input depending on the expected rDS(ON). The input current is mirrored and multiplexed, then digitized by the 6 bit current ADC with an effective input range of 0 to 275A in 4.3A steps. The ADC samples the current in each phase once per switching cycle, and the sampling instant can be varied using a programmable delay, such that sampling in the middle of the ON cycle can be guaranteed.
Switching Frequency
Timing is provided by an on-chip, factory trimmed, temperature compensated oscillator. Additionally, this onchip oscillator can be frequency modulated by a pseudo random pattern to spread the clock spectrum and reduce system electro-magnetic interference (EMI). The ISL6592 operates with a fixed switching frequency (i.e. the switching frequency is fixed independent of load) that is configurable between 300kHz and 1.5MHz. A programmable divider is used to generate the switching frequency, where the frequency is given by: Fsw = 156.25MHz/(2 x div_sel x Nph) where Fsw is the switching frequency, 156.25MHz is the nominal frequency of the timing reference oscillator, div_sel
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The current in the power stage can then be inferred from the current ADC measurement if the drain-source resistance (rDS(ON)) of the FET is known. The rDS(ON) of each FET can be either programmed as a default value, or it can be determined by running the calibration routine either one time at system test or every time the system starts up. Calibration is performed by providing a known current load while the regulator is on and correcting the gain and offset of the current measurement. This requires the use of a precision external current source consisting of a dedicated calibration FET and sense resistor. The ISL6592 senses the voltage across the resistor and provide a variable voltage to drive the gate of the calibration FET, varying its rDS(ON) such that the current through the FET and resistor are under closed loop control. The calibration current and voltage level at which calibration occurs are programmable, and the calibration routine can be bypassed if the default values are to be used. The rDS(ON) value is compensated for temperature drift using either the on-chip temperature sense or an external thermistor that can be placed close to the power stage. The external temperature sense input, TEMP_SEN, is a virtual ground input with a fixed offset of 150mV. An external negative TC thermistor is tied to ground, generating the input current for the measurement. Series resistors or shunt resistors can be used to scale the current. The current range is the same as the current sense inputs, from 0 to 275A in 4.3A steps. Default values should be chosen such that the ADC range is not clipped. The ADC measurements are converted to temperature using a programmable 4-segment piece-wise linear table. The internal proportional-to-absolute temperature (PTAT) reference is digitized directly, using a linear curve fit. Both internal and external temperature measurements are multiplexed through the current ADC at a low frequency, providing run-time internal and external temperature information to perform temperature compensation, reporting, alerts, and shutdown. When used with the ISL6597 integrated power stage, the integrated current sense output can be directly interfaced with the ISL6592 current sense input. The integrated current sense provides superior accuracy, with loadline accuracy comparable to those achieved with series sense resistors. Additionally, the integrated temperature sense in the ISL6597 can be used instead of the external thermistor, providing direct power stage measurements to the system. bandwidths of 10-300kHz to be attained depending on the number and type of power stages used. The effective transfer function of the compensator is given by:
Ki -1 - 1 2 H ( z ) = ----------------- + K p + K d ( 1 - z ) + K d2 ( 1 - z ) -1 1 - z K mod 1 + K fd1 + K fd2 V in ---------------------------------------------------------- ---------------------------------- ------- 1 + K z - 1 + K z - 2 N ph div_sel Q fd1 fd2
where: Ki, Kp, Kd, and Kd2 are the integral, proportional, derivative, and second derivative gain terms Kfd1 and Kfd2 are the coefficients of a second order all pole low pass post-filter Kmod is a programmable maximum duty cycle scaling term Nph is the number of phases and div_sel is the divider ratio setting the switching frequency Vin is the power stage input voltage, typically 12V Q is the ADC step size, 3.125mV The control loop operates at the same frequency as the voltage ADC, which is synchronous to the switching frequency and given by: Fs = 2 * Nph * Fsw = 156.25MHz/div_sel The compensator digital output is converted to a pulse width using a digital counter based pulse width modulator. The pulse width modulator uses 2 successive samples to modulate the leading edge and then the trailing edge of a pulse. The modulator provides for monotonic edge placements with a resolution of 100ps. The next 2 samples are then used to modulate the next phase in the firing sequence. The pulse width modulator is capable of setting a maximum duty cycle limit, overlapping adjacent phases, a minimum pulse width of 13ns, and also producing zero pulse width with minimal glitching.
Voltage Identification Codes
The target voltage is provided by external parallel 6-bit voltage identification (VID) inputs. The VID maps can be configured as either Intel(R) VID, AMD(R), or programmable offset tables. The ISL6592 is fully compliant with VRD/VRM 10.1 and 10.2 deglitching and dynamic VID stepping requirements.
Digital Control Loop and PWM Generation
The digital control loop uses a proportional, integral, and derivative (PID) compensator to drive the digitized sense voltage to the desired target. An additional second derivative gain term and a 2nd order post-filter provide additional high order zeros and poles to further refine the wideband characteristics of the loop. All loop parameters are programmable over a wide range of values, allowing loop
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TABLE 1. OUTPUT VOLTAGE vs INTEL(R) VID CODES VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 VID3 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 VID2 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 VID1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 VID0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 VID5 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VOUT 0.8375 0.8500 0.8625 0.8750 0.8875 0.9000 0.9125 0.9250 0.9375 0.9500 0.9625 0.9750 0.9875 1.0000 1.0125 1.0250 1.0375 1.0500 1.0625 1.0750 1.0875 OFF OFF 1.1000 1.1125 1.1250 1.1375 1.1500 1.1625 1.1750 1.1875 1.2000 VID4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 VID3 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 VID2 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 VID1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 VID0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 VID5 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VOUT 1.2125 1.2250 1.2375 1.2500 1.2625 1.2750 1.2875 1.3000 1.3125 1.3250 1.3375 1.3500 1.3625 1.3750 1.3875 1.4000 1.4125 1.4250 1.4375 1.4500 1.4625 1.4750 1.4875 1.5000 1.5125 1.5250 1.5375 1.5500 1.5625 1.5750 1.5875 1.6000
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TABLE 2. OUTPUT VOLTAGE vs AMD(R) VID CODES VID4 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 VID3 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 VID2 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 VID1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VID5 X X X X X X X X X X X X X X X X VOUT 1.3000 1.3250 1.3500 1.3750 1.4000 1.4250 1.4500 1.4750 1.5000 1.5250 1.5500 OFF 0.8000 0.8250 0.8500 0.8750 VID4 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 VID3 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 VID2 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 VID1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VID5 X X X X X X X X X X X X X X X X VOUT 0.9000 0.9250 0.9500 0.9750 1.0000 1.0250 1.0500 1.0750 1.1000 1.1250 1.1500 1.1750 1.2000 1.2250 1.2500 1.2750
Active Voltage Positioning (AVP)
The AVP loadline can be selected from 4 pre-programmed values using the VRD/M 10.x compliant load line select (LL1 and LL0) inputs. This allows selection of both the loadline slope and the VID setpoint offset. The loadline slope is selectable from 0 to 4m, and the setpoint offset is selectable from 0 to 50mV in 1.56mV steps. The total current is computed by adding the current measured from each phase, then filtering with a single pole programmable filter to set the AVP bandwidth.
Current Balancing/Thermal Balancing
The ISL6592 also uses the channel current measurements to perform current balancing. To minimize thermal gradient effects, each channel adaptively adjusts its current to match the average channel current. The current balance function can also be used to induce a thermal gradient if, for example, some channels have greater cooling capability due to better proximity to airflow. The ISL6592 allows the user to independently force an offset current to each channel, creating a current gradient. This causes the current balance to force the channels with greater cooling capability to supply a higher percentage of the total current, creating a net thermal equilibrium amongst all channels.
current slew rate and minimize spike and droop due to large transient events. Three independent window comparators allows for variation in the number of phases that sink or source. If the transient is slight, only one phase will respond. If the transient is severe, up to three phases respond. This avoids a dramatic sinking or sourcing event, which can cause oscillation. The ISL6592 controller itself uses hysteretic control algorithms after the transient event to ensure that the power stages return to normal operation smoothly with minimal ringing. External-loop ATR provides additional outputs to engage an additional low latency power stage capable of quick charge delivery to the load. This consists of a small FET with a very fast gate driver. Internaland external-loop ATR can be used independently or in conjunction to optimize transient performance.
Output Configurations
The ISL6592 provides 12 configurable outputs that are used to drive up to 6 phase power stages. The outputs can be configured as a single tri-valent pulse width modulated (PWM) signal, or as dual complementary high side control (PWM) and low side control (NDRIVE). In addition, the outputs may also be configured to provide the ex-loop ATR outputs, ATRH to drive a high side undershoot control FET, and ATRL to drive a low side overshoot control FET. For single output configurations, tri-valent FET drivers must be used. The driver input circuit has two thresholds (upper and lower) along with a bias network such that its input is centered between the two thresholds when the ISL6592 output driver is three-stated. This allows three values to be defined for the signal, depending whether the output is high,
Active Transient Response (ATR)
Active Transient Response (ATR) is supported through loadline tracking comparators with programmable thresholds. Both internal- and external-loop ATR are supported. Internalloop ATR engages multiple phases to maximize output 15
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low, or high impedance. If the input signal is high, the gate driver turns the high-side switch on. If the input signal is low, the gate driver turns the low-side switch on. If the input signal is three-state, the driver does not turn either high-side or low-side switches on and the power stage is high impedance or three-stated. Non-overlap circuitry matched to the switch FETs characteristics must be incorporated in the FET driver. For dual output configurations, two independent driver circuits are implemented for the high side and low side. Three-stating the output stage only requires both the PWM and NDRIVE signals to be held logic low. ISL6592 incorporates programmable non-overlap delay, with separate rising edge and falling edge delays, so that the dual driver does not require non-overlap logic. The output drive signals are generated using a 3.3V trivalent driver. All outputs are three-stated during reset, configuration, and inactive state. This allows the user to set the appropriate level to three-state the power stage, using external pull-up or pull-down resistors. ISL6592 also supports independent polarity control on each output, allowing any polarity driver to be used. ISL6592 supporst various output configurations as shown in the Table 3 below.
TABLE 3. PROGRAMMABLE OUTPUT CONFIGURATION NON-SCRAMBLED OUTPUTS (pwm_scramble = 0) # OF PHASES FOR SINGLE PWM OUTPUTS (dual = 0) OUT [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] 2 pwm1 pwm2 hi-Z hi-Z hi-Z hi-Z hi-Z (atrh) hi-Z (atrl) hi-Z hi-Z hi-Z hi-Z 3 pwm1 pwm2 pwm3 hi-Z hi-Z hi-Z hi-Z (atrh) hi-Z (atrl) hi-Z hi-Z hi-Z hi-Z 4 pwm1 pwm2 pwm3 pwm4 hi-Z hi-Z hi-Z (atrh) hi-Z (atrl) hi-Z hi-Z hi-Z hi-Z 5 pwm1 pwm2 pwm3 pwm4 pwm5 hi-Z hi-Z (atrh) hi-Z (atrl) hi-Z hi-Z hi-Z hi-Z 6 pwm1 pwm2 pwm3 pwm4 pwm5 pwm6 hi-Z (atrh) hi-Z (atrl) hi-Z hi-Z hi-Z hi-Z # OF PHASES FOR DUAL PWM/NDRIVE OUTPUTS (dual = 1) 2 pwm1 pwm2 hi-Z ndr1 ndr2 hi-Z hi-Z (atrh) hi-Z (atrl) hi-Z hi-Z hi-Z hi-Z 3 pwm1 pwm2 pwm3 ndr1 ndr2 ndr3 hi-Z (atrh) hi-Z (atrl) hi-Z hi-Z hi-Z hi-Z 4 pwm1 pwm2 pwm3 ndr1 ndr2 ndr3 pwm4 ndr4 hi-Z (atrh) hi-Z (atrl) hi-Z hi-Z 5 pwm1 pwm2 pwm3 ndr1 ndr2 ndr3 pwm4 ndr4 pwm5 ndr5 hi-Z (atrh) hi-Z (atrl) 6 pwm1 pwm2 pwm3 ndr1 ndr2 ndr3 pwm4 ndr4 pwm5 ndr5 pwm6 ndr6
SCRAMBLED OUTPUTS (pwm_scramble = 1) # OF PHASES FOR SINGLE PWM OUTPUTS (dual = 0) OUT [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] 2 pwm1 hi-Z pwm2 hi-Z hi-Z hi-Z hi-Z (atrh) hi-Z (atrl) hi-Z hi-Z hi-Z hi-Z 3 pwm1 hi-Z pwm2 hi-Z pwm3 hi-Z hi-Z (atrh) hi-Z (atrl) hi-Z hi-Z hi-Z hi-Z 4 pwm1 pwm4 pwm2 hi-Z pwm3 hi-Z hi-Z (atrh) hi-Z (atrl) hi-Z hi-Z hi-Z hi-Z 5 pwm1 pwm4 pwm2 pwm5 pwm3 hi-Z hi-Z (atrh) hi-Z (atrl) hi-Z hi-Z hi-Z hi-Z 6 pwm1 pwm4 pwm2 pwm5 pwm3 pwm6 hi-Z (atrh) hi-Z (atrl) hi-Z hi-Z hi-Z hi-Z # OF PHASES FOR DUAL PWM/NDRIVE OUTPUTS (dual = 1) 2 pwm1 ndr1 pwm2 ndr2 hi-Z hi-Z hi-Z (atrh) hi-Z (atrl) hi-Z hi-Z hi-Z hi-Z 3 pwm1 ndr1 pwm2 ndr2 pwm3 ndr3 hi-Z (atrh) hi-Z (atrl) hi-Z hi-Z hi-Z hi-Z 4 pwm1 ndr1 pwm2 ndr2 pwm3 ndr3 pwm4 ndr4 hi-Z (atrh) hi-Z (atrl) hi-Z hi-Z 5 pwm1 ndr1 pwm2 ndr2 pwm3 ndr3 pwm4 ndr4 pwm5 ndr5 hi-Z (atrh) hi-Z (atrl) 6 pwm1 ndr1 pwm2 ndr2 pwm3 ndr3 pwm4 ndr4 pwm5 ndr5 pwm6 ndr6
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Output Firing Sequence
The PWM output and current sense (ISEN) pins of the ISL6592 have been assigned such they can be placed sequentially for PC board layouts (i.e. phase 2 next to 1, phase 3 next to 2, etc...). The output phases are set in a pre-wired firing order to facilitate layout of high phase count systems. For high phase count systems, the VRD layout in the motherboard will likely require the power components to be laid out across two sides of the processor. The firing sequence shown in the table below ensures that for a highly distributed power array, the maximum spatial distribution can be obtained between sequential phases.
TABLE 4. OUTPUT FIRING SEQUENCE 2 3 4 5 6 1 1 1 1 1 2 2 4 4 4 1 3 2 2 2 2 1 3 5 5 FIRING SEQUENCE 1 2 1 3 3 2 3 4 1 6 1 1 2 4 1 2 2 3 2 4 1 3 1 5 2 2 1 4 3 5 1 2 2 1 3 2 ... 3 ... 3 ... 4 ... 6 ...
Shutdown operation also allows a subset of faults to be individually masked. Additionally, the shutdown recovery can be either autonomous or latched. For autonomous recovery, the faults are not latched, so if the fault condition is eliminated when the controller returns to an inactive state, it will wait for a programmable time period, and then attempt a new soft-start. If the fault condition reoccurs, the controller will recommence the shutdown sequence, continuing this cycle indefinitely until the fault condition is eliminated. The programmable delay ensures a sufficiently low duty cycle to prevent the regulator components from being damaged from power cycling, assuming the fault condition itself is not immediately destructive. For latched shutdown, user intervention to clear the latched fault is required before a new soft-start can be attempted. User intervention must come in the form of OUTEN toggle, RESET_N toggle, or controller power cycle. In addition to fault reporting, there are additional fault handling capabilities specific to each fault type that attempts to provide more graceful fault handling than a shutdown, but more active than simply reporting. The specific fault detection capability and alternate fault handling capability is as follows: IUVP: The V12_SEN input continuously senses the +12V supply through a nominally 10:1 resistive divider. A comparator with a programmable threshold is used to indicate an undervoltage condition. IUVP can be used to independently provide either an undervoltage lockout prior to soft-start, or to both provide a lockout and force a shutdown during active regulation. OOVP/OUVP: Programmable comparators continuously monitor the VSEN inputs to detect an output overvoltage or undervoltage condition. The voltage threshold is set relative to VID. OOVP is enabled during soft-start and active regulation, while OUVP is enabled only during active regulation. HSS: The HSS (high-side short) comparator monitors the power stages switch node through the ISEN inputs during the inactive state. If a voltage above 1.0V is detected, the comparator will indicate a HSS detect. If enabled, this will turn all the low side FETs on and prevent the controller from beginning the start-up process. The HSS comparators are disabled in soft-start and active regulation. OCP: The OCP (overcurrent protection) continuously monitors all channel currents to determine whether any of the currents are greater than a programmable threshold. Two mechanisms work independently to control overcurrent conditions. A cycle-by-cycle current limit operates by disabling a channel for one cycle when its current exceeds the threshold. A second mechanism monitors the average current for an overcurrent condition. A programmable threshold sets a current limit at which a steeper loadline is implemented, quickly reducing the output voltage downward
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Fault Detection and Fault Handling
The ISL6592 provides a very flexible fault detection reporting and handling mechanism. Fault detection capability includes: * Input Undervoltage Protection (IUVP) * Output Overvoltage Protection (OOVP) * Output Undervoltage Protection (OUVP) * High-side Short (HSS) * Per Phase Overcurrent Protection (OCP) * Total Output Overcurrent * Two levels of Internal Temperature Protection * Two levels of External Temperature Protection * Configuration Failure * Calibration Range Failure * Calibration Time-out Failure All individual faults are latched and reported over the serial interface. Two configurable fault outputs are provided. Each output allows independent masking of all faults, allowing a subset of faults to be reported over that pin. The outputs can also be configured as either latched or unlatched, active high or active low polarity, and CMOS or open drain outputs. Typical usage of the configurable fault pins would be as a crowbar signal to drive an external crowbar device, temperature alert to notify the system a thermal shutdown is imminent, or as an interrupt to cause a micro-controller to poll the fault registers.
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as the current increases. Both of these mechanisms allow hiccup mode overcurrent protection, where the controller continues to try to provide a regulated output voltage while in overcurrent. Alternatively, a threshold can be set where the overcurrent condition will cause the controller to initiate shutdown. Over-Temperature Alert/Shutdown: Both the internal and external temperature monitors are able to provide fault telemetry in order to shut down the VR in an overtemperature condition. Two programmable thresholds are available for temperature faults. Crossing of the first threshold can be used to only generate a fault report. Crossing the second threshold can be used to cause a shutdown to occur. CRC Failure: The integrity of loading the configuration from the NVM to the controller's registers is checked through a cyclic redundancy code (CRC) check of the data contents. A CRC failure prevents the controller from leaving the inactive state. Calibration Failure: Calibration failures can be detected as either out of range parameter computations or inability to achieve a regulation target in the given time-frame. These failures typically indicate a component is damaged or missing. The master then sends a byte representing the data LS-byte to be written at the current address. The ISL6592 will respond with an Acknowledge. The master then issues a Stop condition, indicating to the ISL6592 that the current transaction is complete. To set the current 16-bit address in the ISL6592, the master sends a control byte with the R/W bit set to 0, indicating a write. If it receives an Acknowledge from the ISL6592, it sends a byte representing the address MS-byte. The ISL6592 will respond with an Acknowledge. The master then sends a byte representing the address LS-byte. The ISL6592 will respond with an Acknowledge. The master then issues a Stop condition, indicating to the ISL6592 that the current transaction is complete. Any read commands issued to the ISL6592 will return data from this address. To read a register from the ISL6592, the master first sets the address to read from. It then sends a control byte with the R/W bit set to 1, indicating a read. If it receives an Acknowledge from the ISL6592 it sends 8 clocks but does not drive the serial data line. The ISL6592 will respond with the MS-byte at the current address. The master will respond with an Acknowledge to indicate to the ISL6592 that the transaction is not yet complete. The master again sends 8 clocks but does not drive the serial data line. The ISL6592 will respond with the LS-byte at the current address. The master will respond with a Not Acknowledge to indicate to the ISL6592 that the transaction is complete. The ISL6592 will stop driving the serial data line. The master then issues a Stop condition to indicate that the transaction is complete. If the ISL6592 has started an internal operation in response to a transaction on the I2C bus (register read/write, flash write, flash page erase) but the operation has not completed before the last Acknowledge slot in the I2C bus protocol, the ISL6592 will add wait states by stretching the low portion of the last clock cycle. This also occurs in response to read/write requests to addresses that do not support physical memory in the ISL6592. In this case, the ISL6592 will add wait states until an internal watchdog timer expires, and the I2C bus is guaranteed to be released.
I2C Interface
All operating parameters in the ISL6592 is configurable via the I2C interface. Status can also be read back via the same interface. The ISL6592 operates as a slave at a standard speed of 100kHz. Three transactions are supported on the I2C interface: 1) Set current address, 2) Write register, 3) Read register from current address. All transactions start with a control byte sent from the I2C master device. The control byte begins with a Start condition, followed by 7-bits of slave address. The last bit sent by the master is the R/W bit and is 0 for a write. If any slaves on the I2C bus recognize their address, they will Acknowledge by pulling the serial data line low for the last clock cycle in the control byte. If no slaves exist at that address or are not ready to communicate, the data line will be 1, indicating a Not Acknowledge condition. The ISL6592 address on the I2C bus is 1110_000 or 1110_001, with the LSB set by the input pin SADDR. To write a register in the ISL6592, the master sends a control byte with the R/W bit set to 0, indicating a write. If it receives an Acknowledge from the ISL6592, it sends a byte representing the address MSB. The ISL6592 will respond with an Acknowledge. The master then sends a byte representing the address LSB. The ISL6592 will respond with an Acknowledge. The master then sends a byte representing the data MS-byte to be written at the current address. The ISL6592 will respond with an Acknowledge. 18
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I2C Read and Write Protocol
Data write S slave_addr + W A reg_addr MSB A reg_addr LSB A reg_data MSB A reg_data LSB A P
Set current address S slave_addr + W A reg_addr MSB A reg_addr LSB A P
Read from current address S slave_addr + R A reg_addr MSB A reg_addr LSB N P
Driven by master
Driven by slave
Key Registers
Table 5 below provides brief descriptions of several key configuration (R/W - read/write) and status (RO - read only) registers available on the ISL6592 Digital Multiphase Controllers.
TABLE 5. KEY REGISTERS RANGE REGISTER isum_avg[18:0] vavp_avg_mon[9:0] kavp_XX[9:0] load_line_offset_XX[4:0] kavp_limit_XX[9:0] isum_max_XX[7:0] DESCRIPTION VR load current. Averaged sum of all channel current data over a user programmable averaging window (default = 16ms) AVP output voltage. Averaged VAVP monitored value ADC voltage. AVP loadline slope. Nominal value of load line slope resistance input for case LL1 = X, LL0 = X. AVP loadline VID offset. VID set-point load-line offset tolerance voltage for case LL1 = X, LL0 = X. Secondary overcurrent limit AVP loadline slope. Overcurrent load line slope resistance input for case LL1 = X, LL0 = X. Overcurrent limit. Max load current threshold for secondary slope roll-off of AVP voltage or overcurrent shutdown for case LL1 = X, LL0 = X. PTAT Temperature. Averaged PTAT calibration temperature output. PTAT alert temperature. PTAT sensor alert temperature reference. PTAT shutdown temperature. PTAT sensor shutdown temperature reference. Thermistor temperature. Averaged Thermistor monitor temperature output. Thermistor alert temperature. Thermistor sensor alert temperature reference. Thermistor shutdown temperature. Thermistor sensor shutdown temperature reference. Input undervoltage threshold. IUVP comparator threshold fixed at 0.975V Output overvoltage protect threshold. Tracking VID overvoltage threshold for case LL1 = X, LL0 = X. Output undervoltage protect threshold fixed at 0.6V FORMAT RO RO R/W R/W R/W R/W MIN 0.00A 0.0mV 0.0 0.0V 0.0 0.0A MAX 524.288A 3,196.875mV 3.902m 48.4375mV 15.610m +204.0A RESOLUTION 1mA 3.125mV 0.003815m 1.5625mV 0.01526m 0.800A
ptat_mon[5:0] ptat_alert_ref[5:0] ptat_shutdown_ref[5:0] temp_mon[5:0] therm_alert_ref[5:0] therm_shutdown_ref[5:0] iuvp_thresh[5:0] oovp_limit_XX[5:0] ouvp_limit_XX[5:0]
RO R/W R/W RO R/W R/W R/W R/W R/W
0C 0C 0C 0C 0C 0C n/a 0.0mV n/aV
157.5C 157.5C 157.5C 157.5C 157.5C 157.5C .975V 787.5mV 600mV
2.5C 2.5C 2.5C 2.5C 2.5C 2.5C 0.25V 12.5mV 12.5mV
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FN9163.1 August 5, 2005
ISL6592
TABLE 5. KEY REGISTERS (Continued) RANGE REGISTER pwm_scramble DESCRIPTION PWM scramble select. Controls mapping of PWM and NDRIVE signals to pins OUT1 through OUT12. See Table 3 herein for details. PWM/NDRIVE select. 0 = Only PWM outputs active for use with single input drivers 1 = PWM & NDRIVE outputs active for use with dual input drivers Fault1 pin output masks. Inputs are enabled for reporting when set to logic 1. If multiple inputs are selected, output is "OR" of selected input signals. 17 = NVM fault 16 = Internal bus fault 15 = IUVP 14 = OUVP 13 = OOVP 12 = thermistor temp alert 11 = thermistor temp shutdown 10 = PTAT temp alert 9 = PTAT temp shutdown 8 = channel 1 high side short 7 = channel 2 high side short 6 = channel 3 high side short 5 = channel 4 high side short 4 = channel 5 high side short 3 = channel 6 high side short 2 = unused 1 = MHz controller fault 0 = Calibration fault Shutdown control mask. Inputs are enabled for shutdown when set to logic 1. If multiple inputs are selected, output is "OR" of selected input signals. 15 = IUVP 14 = OUVP 13 = OOVP 12 = Individual phase current fault during active regulation 11 = thermistor temp shutdown 10 = Individual phase current fault during soft-start 9 = PTAT temp shutdown 8 = channel 1 high side short 7 = channel 2 high side short 6 = channel 3 high side short 5 = channel 4 high side short 4 = channel 5 high side short 3 = channel 6 high side short 2 = Total current fault during active regulation 1 = Total current fault during soft-start 0 = Calibration fault Channel mask. Selects number of active phases. Phases must be selected in sequential order. 000011 = 2-phase operation 000111 = 3-phase operation 001111 = 4-phase operation 011111 = 5-phase operation 111111 = 6-phase operation FORMAT MIN MAX RESOLUTION
dual
fault1_mask[17:0] fault2_mask[17:0]
shutdown_mask[15:0]
ch_mask[6:1]
20
FN9163.1 August 5, 2005
ISL6592 Thin Plastic Quad Flatpack Packages (LQFP)
D D1 -D-
Q48.7x7A (JEDEC MS-026BBC ISSUE B) 48 LEAD THIN PLASTIC QUAD FLATPACK PACKAGE
INCHES SYMBOL A A1 A2 MIN 0.002 0.054 0.007 0.007 0.350 0.272 0.350 0.272 0.018 48 0.020 BSC MAX 0.062 0.005 0.057 0.010 0.009 0.358 0.280 0.358 0.280 0.029 MILLIMETERS MIN 0.05 1.35 0.17 0.17 8.90 6.90 8.90 6.90 0.45 48 0.50 BSC MAX 1.60 0.15 1.45 0.27 0.23 9.10 7.10 9.10 7.10 0.75 NOTES 6 3 4, 5 3 4, 5 7 Rev. 2 1/99 NOTES: 1. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 2. All dimensions and tolerances per ANSI Y14.5M-1982. 3. Dimensions D and E to be determined at seating plane -C- .
0.08 0.003 M C A-B S DS b b1 0.09/0.16 0.004/0.006 BASE METAL WITH PLATING
-AE E1
-B-
b b1 D D1 E
e
PIN 1 SEATING A PLANE 0.08 0.003 -C-
E1 L N e
-H-
4. Dimensions D1 and E1 to be determined at datum plane -H- . 5. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm (0.010 inch) per side. 6. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08mm (0.003 inch). 7. "N" is the number of terminal positions.
11o-13o 0.020 0.008 MIN 0o MIN GAGE PLANE L 0o-7o 0.25 0.010 11o-13o A2 A1
0.09/0.20 0.004/0.008
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 21
FN9163.1 August 5, 2005

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